Browsing by Author "55387"
Now showing items 1-13 of 13
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3D FPGA versus multiple FPGA system : enhanced parallelism in smaller area
Nunna, K.C.; Madipour, Farhad; Murakami, K.J. (2014-01)Handling large amounts of data is being limited by bandwidth constraint between processors components and their memory counterparts. Three-dimensional integration (3D) is providing possible solution to handle such critical ... -
Analysis of NTP DRDoS attacks’ performance effects and mitigation techniques
Sarrafpour, Bahman; Abbaro, C.; Pitton, I.; Young, C.; Madipour, Farhad (2016-12-14)Denial of Service (DoS) attacks are a type of interruption (malicious and/or unintended) that restrict or completely deny services meant for legitimate users. One of the most relevant DoS attacks is Distributed Denial of ... -
Collaborative teams : [The investigation of how collaborative processes and team dynamics impact on collaborative teaching in a New Zealand context]
Baker, Karen; Rowley, Rich; Madipour, Farhad (2016-10)The focus of this research in progress is to explore teachers’ perceptions of the nature and impact of collaborative teaching by specifically addressing practice-based collaborative interactions. The main question that ... -
A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias
Said, M.; Shalaby, A.; Madipour, Farhad; Morteza, B.; El-Sayed, M. (Elsevier, 2016)The use of short Through-Silicon Vias (TSVs) in 3D integration Technology introduces a significant reduction in routing area, power consumption, and delay. Although, there are still several challenges in 3D integration ... -
A design methodology for performance maintenance of 3D Network-on-Chip with multiplexed Through-Silicon Vias
Madipour, Farhad; El-Sayed, M.; Murakami, K.J.; Said, M. (ACM DL (Digital Library), 2015-06)3D integration is an emerging technology that overcomes 2D integration process limitations. The use of short Through-Silicon Vias (TSVs) introduces a significant reduction in routing area, power consumption, and delay. ... -
A Highly Parallel SAD Architecture for Motion Estimation in HEVC Encoder
Medhat, Ahmed; Shalaby, Ahmed; Sayed, Mohammed S.; Elsabrouty, Maha; Madipour, Farhad (2014-11)The high computational cost of the motion estimation module in the new HEVC standard raises the need for efficient hardware architectures that can meet the real-time processing constraint. In addition, targeting HD and UHD ... -
Keep-Out-Zone analysis for three-dimensional ICs
Said, M.; Madipour, Farhad; El-Sayed, Mohamed (Institute of Electrical and Electronics Engineers (IEEE), 2014-04)One of main challenges of 3D-integration is the area overhead which has two main causes: first the huge TSV diameter which is usually in the range of microns, and the second reason is the Keep-Out-Zone (KOZ) overhead due ... -
Modeling the impact of clustering on the lifetime of wireless sensor networks
Madipour, Farhad; Rahman, M.F.; Murakami, K.J. (2015-03)Energy efficiency and network lifetime are the most critical issues for Wireless Sensor Networks (WSNs). Clustering is one of the well-known techniques for reducing energy consumption of the network and improving its ... -
A neuro-fuzzy fan speed controller for dynamic thermal management of multi-core processors
Abad, Javad Mohebbi Najm; Salami, Bagher; Noori, Hamid; Soleimani, Ali; Madipour, Farhad (ACM DL (Digital Library), 2014-05)Cooling equipments is a thermal management technique that reduces the thermal resistance of the heat sink without any performance degradation. However, higher fan speed produces a lower thermal resistance, but at the expense ... -
Physical-aware predictive dynamic thermal management of multi-core processors
Salami, Bagher; Noori, Hamid; Madipour, Farhad; Baharani, Mohammadreza (Elsevier, 2016-03-30)The advances in silicon process technology have made it possible to have processors with larger number of cores. The increment of cores number has been hindered by increasing power consumption and heat dissipation due to ... -
A physical-aware task migration algorithm for dynamic thermal management of SMT multi-core processors
Madipour, Farhad (South Asia Pacific - Design Automation Conference, 2014-01)This paper presents a task migration algorithm for dynamic thermal management of SMT multi-core processors. The unique features of this algorithm include: 1) considering SMT capability of the processors for task ... -
A reconfigurable data-path accelerator based on single-flux quantum circuits
Kataoka, H.; Honda, H.; Madipour, Farhad; Yoshikawa, N.; Fujimaki, A.; Akaike, H.; Takagi, N.; Murakami, K.J. (Institute of Electrical and Electronics Engineers (IEEE), 2014-03)The single-flux quantum (SFQ) is expected to be a next-generation high-speed and low-power technology in the field of logic-circuits. CMOS as the dominant technology for conventional processors cannot be replaced with SFQ ... -
A survey on big data processing infrastructure: evolving role of FPGA
Nunna, K.C.; Madipour, Farhad; Trouve, A.; Murakami, K.J. (InderScience Publishers, 2015)In today’s commercial world, information is becoming a major economic resource thus leading to a statement - Information is wealth. It is a technical challenge for computer systems in managing and analyzing the large volumes ...