Browsing by Collaborator "Egypt-Japan University of Science and Technology (Alexandria, Egypt)"
Now showing items 1-2 of 2
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A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias
(Elsevier, 2016)The use of short Through-Silicon Vias (TSVs) in 3D integration Technology introduces a significant reduction in routing area, power consumption, and delay. Although, there are still several challenges in 3D integration ... -
A Highly Parallel SAD Architecture for Motion Estimation in HEVC Encoder
(2014-11)The high computational cost of the motion estimation module in the new HEVC standard raises the need for efficient hardware architectures that can meet the real-time processing constraint. In addition, targeting HD and UHD ...
