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dc.contributor.authorSaid, M.
dc.contributor.authorShalaby, A.
dc.contributor.authorMadipour, Farhad
dc.contributor.authorMorteza, B.
dc.contributor.authorEl-Sayed, M.
dc.date.accessioned2017-05-31T02:55:11Z
dc.date.available2017-05-31T02:55:11Z
dc.date.issued2016
dc.identifier.issn0141-9331
dc.identifier.urihttps://hdl.handle.net/10652/3758
dc.description.abstractThe use of short Through-Silicon Vias (TSVs) in 3D integration Technology introduces a significant reduction in routing area, power consumption, and delay. Although, there are still several challenges in 3D integration technology; mainly low yield, which is a direct result of extra fabrication steps of TSVs. Therefore, reducing TSV count has a considerable effect on improving yield and hence reducing cost. A TSV multiplexing technique called TSVBOX was introduced in [1] to reduce the TSV count without affecting the direct benefits of TSVs. Although, the TSVBOX introduces some delay to the signals to be multiplexed, this delay effect of TSV multiplexing is not addressed yet. In this paper, we analyze the TSVBOX timing requirements and propose a design methodology for TSVBOX-based 3D Network-on-Chip (NoC). Then performance and power comparisons are conducted to investigate the direct effects of TSV multiplexing on these two metrics. After that the basic fabrication metrics are compared to investigate the effect of the proposed design methodology on yield and cost. We show that the TSVBOX extremely enhances the fabrication metrics at minimal degradation in performance and power consumption, especially for Hotspot-like traffic patternsen_NZ
dc.language.isoenen_NZ
dc.publisherElsevieren_NZ
dc.relation.urihttp://www.sciencedirect.com/science/article/pii/S0141933116000156en_NZ
dc.subject3D Network-on-Chipen_NZ
dc.subjectfabricationen_NZ
dc.subjectThrough-Silicon Vias (TSVs)en_NZ
dc.titleA design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Viasen_NZ
dc.typeJournal Articleen_NZ
dc.date.updated2017-05-10T05:39:15Z
dc.rights.holderElsevieren_NZ
dc.subject.marsden090604 Microelectronics and Integrated Circuitsen_NZ
dc.identifier.bibliographicCitationSaid, M., Shalaby, A., Mehdipour, F., Morteza, B., & El-Sayed, M. (2016). A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias. Microprocessors and Microsystems, 43, pp.26-46. doi:10.1016/j.micpro.2016.01.011en_NZ
unitec.publication.spage26en_NZ
unitec.publication.lpage46en_NZ
unitec.publication.volume43en_NZ
unitec.publication.titleMicroprocessors and Microsystemsen_NZ
unitec.peerreviewedyesen_NZ
dc.contributor.affiliationUniversity of Aucklanden_NZ
dc.contributor.affiliationEgypt-Japan University of Science and Technology (Alexandria, Egypt)en_NZ
dc.contributor.affiliationAssiut University (Assiut, Egypt)en_NZ
dc.contributor.affiliationKyushu University (Fukuoka, Japan)en_NZ
unitec.identifier.roms59458en_NZ
unitec.institution.studyareaConstruction + Engineering


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